The present invention generally relates to a semiconductor fabrication technique for forming metal gates and more particularly, relates to a method for fabricating metal gates in deep sub-micron devices such as CMOS with substantially reduced fabrication steps.
In the recent trend of continuing size reductions in semiconductor fabrication, the application of CMOS devices has been the main development trend to fulfill the size reduction requirement. In fabricating a CMOS device that consists of a PMOS and an NMOS, the fabrication steps are complicated in order to produce gate electrodes meeting different requirements for the PMOS and NMOS. To achieve a stable threshold voltage for the CMOS device, the gate electrodes that must be formed on the n-type semiconductor base for the PMOS and on the p-type semiconductor base for the NMOS must be fabricated of different materials. The different materials required in forming the gate electrodes for the PMOS and the NMOS necessarily increase the fabrication steps for deposition, lithography and etching.
For instance, in the fabrication of a PMOS, the electrically conductive material used in forming the gate electrodes must have a work function in-between the values of 4.8-5.5 eV. On the other hand, the electrically conductive material used in forming the gate electrodes for the NMOS must have a work function in-between 4.0-4.5 eV. In the present available technology wherein a polysilicon gate material is utilized in forming sub-micron devices, implantation density can be adjusted in doping the polysilicon gates for the PMOS and NMOS by using a series of photoresist layers as masks. However, when future deep sub-micron devices are designed with metal gate electrodes replacing the polysilicon gate electrodes, the fabrication processes required for different metals that have different work functions is much more complicated. For instance, the use of two different metals for the gate electrodes requires two separate deposition processes, two separate photomasking and photoresist patterning, two separate etching processes for patterning, two separate steps for removing photoresist layers, and two separate cleaning/rinse procedures, etc. The complicated processes lead to high cost and low yield which are not acceptable in designing a modern fabrication process.
It is therefore an object of the present invention to provide a method for fabricating metal gates for deep sub-micron CMOS devices that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide method for fabricating metal gates for deep sub-micron CMOS devices that has substantially reduced processing steps.
It is a further object of the present invention to provide a method for fabricating metal gates for deep sub-micron CMOS devices by using a pure metal and a metal nitride that have different work functions as the gate electrode materials.
It is another further object of the present invention to provide a method for fabricating metal gates for deep sub-micron CMOS devices wherein a transition metal nitride is used for forming the gate electrode for PMOS while pure transition metal is used in forming gate electrode for NMOS.
It is still another object of the present invention to provide a method for fabricating metal gates for deep sub-micron CMOS devices which only requires a single metal deposition, a single masking, a single photoresist patterning and a single etching process.
In accordance with the present invention, a method for fabricating metal gates in deep sub-micron CMOS devices is provided.
In a preferred embodiment, a method for fabricating metal gates in deep sub-micron CMOS devices can be carried out by the operating steps of providing a pre-processed silicon substrate that has an active area formed on a top surface, the active area includes a PMOS and an NMOS; depositing a gate dielectric layer on the active area of the silicon substrate; blanket depositing a transition metal nitride on the top surface of the substrate; patterning the transition metal nitride to cover the gate dielectric layer only; depositing and patterning a cap layer on top of the PMOS; annealing the substrate by a rapid thermal process at a temperature between about 300xc2x0 C. and about 700xc2x0 C., whereby nitrogen evaporates away from the transition metal nitride that is not shielded by the cap layer such that only a transition metal covers the NMOS; and removing the cap layer from top of the PMOS.
The method for fabricating metal gates in deep sub-micron CMOS devices may further include the step of, after removing the cap layer from top of the PMOS, planarizing the transition metal nitride layer and the transition metal layer by chemical mechanical polishing. The gate dielectric layer deposited may be silicon oxide, silicon oxynitride or silicon nitride. The transition metal nitride may be deposited by a physical vapor deposition technique. The transition metal nitride may be WNx. The transition metal nitride may also be deposited by a chemical vapor deposition technique. The cap layer may be deposited by a plasma enhanced chemical vapor deposition technique from a material of Si3N4, SiC, SiO2 or SiON.
In the method for fabricating metal gates in deep sub-micron CMOS devices, the rapid thermal process carried out for annealing the transition metal nitride layer may be conducted in vacuum at a temperature preferably between about 350xc2x0 C. and about 600xc2x0 C., and more preferably between about 400xc2x0 C. and about 500xc2x0 C. The rapid thermal process may be carried out in an environment of inert gas, such as N2, He or Ar. The rapid thermal process may be carried out for a time period between about 1.5 min. and about 20 min. The gate electrode material may include all transition metals such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Cr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, La, Hf, Ta, W, Re, Os, Ir, Pt and Au.